Intel’s new technology : The Itanium 2

Ravi Madapati 
Faculty Member
Icfai Knowledge Center

Intel's Itanium processors were 64-bit chips, specifically designed for high-end enterprise and high-performance applications. The Itanium 2 processor was the second in the Itanium processor family. Intel faced major challenges in gaining acceptance for Itanium. Intel had put tremendous amounts of energy and money behind Itanium. Intel's IA-64 fund, started by Intel for encouraging the use of Intel architecture, had invested heavily in start-ups to assist them in developing Itanium-based applications and worked extensively with established hardware and software
manufacturers to get them involved in Itanium-based projects. Would Itanium 2 also share the same fate as Itanium 1 or would the tech world embrace this new processor? The article illustrates the challenges involved in gaining market acceptance for a new technology.

In early 2003, Intel, the largest producer of microprocessors in the world, launched the company’s new 64-bit microprocessor, the Itanium 2. Intel spent billions of dollars on Itanium 2 to take on IBM and Sun Microsystems [Sun] in the $25 bn market for the 64-bit servers.

The processor also boasts advanced reliability features, including extensive error detection and correction on the processor’s major data structures. Itanium 2 also has an advanced Machine Check Architecture for intelligent error management and recovery of complex platform errors to prevent data loss, corruption and down time.

The Itanium 2 is also socket-compatible with two future generations of Itanium family processors to allow them to be easily swapped into existing Itanium 2-based systems. This extended the value and longevity of customer investments in Itanium 2-based platforms. In addition, Intel has five future Itanium processor family products in development, with designs already underway that reached into the second half of the decade. But Intel faced major challenges in gaining acceptance for 64-bit chips. The shift to 64-bit computing is not merely a matter of upgrading the Pentium. Itanium 2 requires computer makers to redesign their hardware and software companies, effectively requiring them to rewrite all their code. While Itanium I has been a failure, the timing of the launch of Itanium 2 is a cause for concern. Following the dotcom crash, the tech market is witnessing a major downturn.

The Itanium 2

The Itanium 2 processor has been designed for demanding enterprise and technical applications. Intel claimed the processor offered up to 50% higher transaction processing performance than comparable platforms from Sun Microsystems [Sun] and at lower costs. Intel also believes Itanium provided flexibility and choice through the support of a wide range of operating systems, including Windows, HP, and Linux and via a growing base of applications targeted at high-end enterprise and technical computing environments. Itanium 2 offers as much as twice the performance of its parent chip, the Itanium 1. Itanium 2 enables computer manufacturers to build either four- or eight-way Itanium 2 servers. A Scalability Port enables manufactures to expand outwards into configurations beyond eight-way systems. The Scalability Port (SP) is a point-to-point cache consistent interface to build scalable-shared memory multiprocessors. The SP interface consists of three layers of abstraction:

The Physical Layer, the Link Layer and the Protocol Layer. The Physical Layer uses pin-efficient simultaneous bi-directional signaling and operated at 800 MHz in each direction. The Link Layer supports virtual channels and provided flow control and reliable transmission. The Protocol Layer implements cache consistency, synchronization, and interrupt delivery functions among others. The first implementation of the SP interface is in the Intel’s E8870 and E9870 chipset for the Intel Itanium 2 processor and future generations of the Itanium processor family. The E8870 chipset is the first of a new generation of chipset architecture, specifically designed to meet the needs of high-end server platform segments. The E8870 chipset, optimized for the Itanium 2 processor, provides new levels of performance, scalability, and enhanced error detection, correction and containment. Forward-compatibility with future versions of the Itanium processor family is also a feature of the Itanium 2 processor.

Itanium 2 is fabricated on an .18-micron process, similar to Itanium, and initially shipped at 900MHz and 1GHz. The top clock speed is only 25% faster than the Itanium but Itanium 2 demonstrated 1.5 times performance improvements in applications over Itanium. The improved performance is due to both micro-architectural improvements and chip/platform bandwidth enhancements. One of the biggest performance enhancers is the L3 cache being on-die in Itanium 2 versus off-die in Itanium^[3] . As a result, significant reduction in latencies and increase in bandwidth is possible.

Itanium 2 could only process six instructions (two bundles of three instructions each) at once, similar to Itanium 1, but Itanium 2 could handle more diverse groupings of instructions. Though IA-64 supported a 64-bit address space, and Itanium 2 supported 64-bit virtual memory addressing, it only supported 50-bits of physical address pins and larger than the 44 bits of physical addressing on the Itanium. Intel claimed four customer-specific chipsets would support the Itanium 2: The HP zx1; the Hitachi ColdFusion-2 (CF-2); the IBM Enterprise X-Architecture’s “Summit” chipset; and an unnamed NEC Itanium chipset. In addition, Groupe Bull and Unisys were adapting the E8870 architecture to develop customized systems. The companies designing Itanium 2 chipsets represented first-generation Itanium customers. In total, counting some unannounced products, Intel believed nine chipsets supported the Itanium 2.

[1] EPIC technology breaks through the sequential nature of conventional processor architectures by allowing the software to communicate explicitly to the processor when operations can be done in parallel. Reducing the number of branches and branch mispredicts, and reducing the effects of memory-to-processor latency has increased performance. EPIC technology also reduces hardware complexity. EPIC was jointly designed by Intel and HP and introduced in 1997.

[2] Three levels of cache reduce memory latency; Level 1 cache, Level 2 cache and Level 3 cache. 3 MB Level 3 cache is a pool of memory integrated into the processor for performance level of 3 MB.

[3] Level 3 cache is shifted on to the die itself in Itanium 2, which increases the performance of the processor. In Itanium 2, this is off-die, which means it is not cast on the microprocessor.

© Icfai Press. Global CEO • August 2003, All Rights Reserved.