Intel's New Technology: The Itanium 2
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Keywords
Itanium 2 processor, microprocessors, high-end enterprise, business intelligence, databases, enterprise resource planning, SCM, computing, computer-aided engineering
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The Itanium 2
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The Itanium 2 processor has been designed for demanding enterprise and technical applications. Intel claimed the processor offered up to 50% higher transaction processing performance than comparable platforms from Sun Microsystems [Sun] and at lower costs. Intel also believes Itanium provided flexibility and choice through the support of a wide range of operating systems, including Windows, HP, and Linux and via a growing base of applications targeted at high-end enterprise and technical computing environments. Itanium 2 offers as much as twice the performance of its parent chip, the Itanium 1. Itanium 2 enables computer manufacturers to build either four- or eight-way Itanium 2 servers. A Scalability Port enables manufactures to expand outwards into configurations beyond eight-way systems. The Scalability Port (SP) is a point-to-point cache consistent interface to build scalable-shared memory multiprocessors. The SP interface consists of three layers of abstraction: The Physical Layer, the Link Layer and the Protocol Layer. The Physical Layer uses pin-efficient simultaneous bi-directional signaling and operated at 800 MHz in each direction. The Link Layer supports virtual channels and provided flow control and reliable transmission. |
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The Protocol Layer implements cache consistency, synchronization, and interrupt delivery functions among others. The first implementation of the SP interface is in the Intel's E8870 and E9870 chipset for the Intel Itanium 2 processor and future generations of the Itanium processor family. The E8870 chipset is the first of a new generation of chipset architecture, specifically designed to meet the needs of high-end server platform segments. The E8870 chipset, optimized for the Itanium 2 processor, provides new levels of performance, scalability, and enhanced error detection, correction and containment. Forward-compatibility with future versions of the Itanium processor family is also a feature of the Itanium 2 processor. Itanium 2 is fabricated on an .18-micron process, similar to Itanium, and initially shipped at 900MHz and 1GHz. The top clock speed is only 25% faster than the Itanium but Itanium 2 demonstrated 1.5 times performance improvements in applications over Itanium. The improved performance is due to both micro-architectural improvements and chip/platform bandwidth enhancements. One of the biggest performance enhancers is the L3 cache being on-die in Itanium 2 versus off-die in Itanium3. As a result, significant reduction in latencies and increase in bandwidth is possible.
Itanium 2 could only process six instructions (two bundles of three instructions each) at once, similar to Itanium 1, but Itanium 2 could handle more diverse groupings of instructions. Though IA-64 supported a 64-bit address space, and Itanium 2 supported 64-bit virtual memory addressing, it only supported 50-bits of physical address pins and larger than the 44 bits of physical addressing on the Itanium. Intel claimed four customer-specific chipsets would support the Itanium 2: The HP zx1; the Hitachi ColdFusion-2 (CF-2); the IBM Enterprise X-Architecture's "Summit" chipset; and an unnamed NEC Itanium chipset. In addition, Groupe Bull and Unisys were adapting the E8870 architecture to develop customized systems. The companies designing Itanium 2 chipsets represented first-generation Itanium customers. In total, counting some unannounced products, Intel believed nine chipsets supported the Itanium 2.
3] Level 3 cache is shifted on to the die itself in Itanium 2, which increases the performance of the processor. In Itanium 2, this is off-die, which means it is not cast on the microprocessor.